A clock mesh network has been the preferred clock network structure for high-end microprocessor design because of its tolerance to variations. The variation tolerance is achieved by placing the redundant mesh grid wires near the sink registers, but at the cost of power dissipation.  To overcome the limitations of existing clock mesh networks, a team of Drexel researchers has developed a clock mesh network synthesis method which enables clock gating on the local sub-trees of the clock mesh network in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path of the design area. The method encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. With gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The method has modes of low power and high performance to serve different design purposes.