Power supply noise management continues to be a challenge with the scaling of CMOS technologies. The increasing power density and, therefore, current consumption of high-performance ICs, results in increased challenges in the design of a reliable and efficient on-chip power delivery network. If the power supply voltage droops too low, circuit performance and functionality can be compromised. Moreover large overshoots can have circuit reliability implications, such as electromigration issues and degradation of the gate oxide of transistors, in addition to compromising functionality. The most commonly employed technique to suppress this power supply noise is thru the use of on-chip decoupling capacitor (decap), but is known to have significant associated area and leakage costs.

Researchers at Drexel have now developed a novel power-supply noise suppression technique through the use of hyperabrupt junction tuning varactor diode as decoupling capacitor (decap) for noise critical digital blocks. With the use of this innovative technique, the voltage droops and overshoots on the on-chip power distribution network can be suppressed by up to 60% as compared with existing adaptive clocking, MIM or deep trench decaps of the same capacitance. In addition, there is no added latency to react to power supply noise, and there is no degradation to circuit performance as compared with existing techniques in commercial products. Moreover detection of a noise event is not needed, which is a requirement with all of existing noise mitigation techniques.