Methods and Computer-Readable Media for Synthesizing a Multi-Corner Mesh-Based Clock Distribution Network for Multi-Voltage Domain and Clock Meshes and Integrated Circuits

Overview

One aspect of the invention provides a including: (a) placing N×N max size buffers at an (n−1)st level of one of the voltage domains i until a maximum slew slewmax within the voltage domain i exceeds a defined slew threshold; (b) calculating maximum insertion delay values for all cases for each of the voltage domains; (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j: (i) adding a max size buffer to all voltage domains except voltage domain j; and (ii) repeating steps (b) and (c); (d) reducing buffer sizes for each of the voltage domains; (e) recalculating maximum insertion delay values; and (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.

Intellectual Property and Development Status

United States Patent Pending- 14/697,864

Commercialization Opportunities

 

Contact Information

 

Robert B. McGrath, Ph.D.

Senior Associate Vice Provost

Office of Technology Commercialization

Drexel University

3180 Chestnut Street, Ste. 104

The Left Bank

Philadelphia, PA 19104

Phone: 215-895-0303

Email: RBM26@Drexel.edu

 

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