Integrated Circuits (ICs), which serve as the keystone of modern electronic devices, are increasingly vulnerable to third party tampering due to the industry’s increasing reliance on untrusted third-party foundries in the IC design flow. The result is a growing concern of IC reliability and security, with threats that include: IC counterfeiting, intellectual property (IP) theft, IC overproduction, and the insertion of hardware Trojans.  To mitigate these threats, researchers have explored the use of logic encryption, however existing methods, such as XOR and look-up table (LUT) based logic encryption suffer drawbacks in high per-gate overheads in power, area and performance.  To overcome these deficiencies, a team of Drexel researchers have developed two separate gate level logic encryption techniques aimed at ensuring the reliability and security of ICs in critical applications while achieving markedly lower power, area, and performance overhead. In particular, the team has developed two techniques including:  1) Modifications to standard CMOS cells to include key transistors, and 2) transmission gate logic encryption, which also includes key inputs to the gate.    Relative to the best known approach (XOR based implementation of the encrypted AND) both methods yield similar improvements with a power reduction of 43.2%, an estimated area reduction of 19.8%, and a performance increase of 46.9%.