Reduction in power consumption without sacrificing processing speed is increasingly important objective in integrated circuit design nowadays. Power distribution of the clock net contributes a large fraction of the total power consumption. Thus, the generation and distribution of this clock signal is one of the most critical steps in designing an integrated circuit. For a circuit to function correctly, clock pulses must arrive nearly simultaneous at the clock pins of all clocked components. The difference in arrival times between a single pulse arriving at two different clocked components is referred to as clock skew which must be within a certain tolerance. Current commercial integrated circuit design flows have clock tree synthesis stages that are optimized to satisfy selected clock skew targets. Clock slew is a secondary objective, and typically corrected with post-CTS optimization through additional wiring and buffering (among other techniques).

Researchers at Drexel have developed a new approach to clock tree synthesis, where clock skew is considered a priority for a given clock skew budget. This innovative approach automatically generates a clock tree that not only satisfies the challenging clock slew constraints for newer CMOS technologies, but it also generates trees that consume much less power compared to those generated by current commercial tools. The proposed methodology is implemented in a software code that works seamlessly with commercial integrated circuit design flows( e.g. Cadence and Synopsys ). Considering the significance of power consumption in modern electronics that need higher clock frequencies (with tighter clock slew constraints), this invention has the potential to becoming a stable of each integrated circuit design flow.